RISC-V Spring Ecosystem Meetup

Bay Area RISC-V Group
Mon, Jun 21, 10:00 AM (PDT)

88 RSVP'ed

This virtual meetup will feature Mark Himelstein, the CTO of RISC-V International and Lattice Semiconductor. Join us for this event on June 21 at 10am PT.

About this event

Post event slides available here!

We look forward to updating the broader technical community on the latest progress of RISC-V.  Mark Himelstein, the CTO of RISC-V will present on the latest progress various technical tasks groups have made. In addition, Lattice Semiconductor will present on their recently announced RISC-V offerings, including their design tools and security examples using RISC-V in Lattice FPGAs.  

10-10:10 Upcoming RISC-V community event updates - Ted Marena

10:10-10:40 RISC-V technical progress - Mark Himelstein

10:40-11:00  Lattice Semicondutor RISC-V design tools & examples - Roger Do, Eric Sivertson

Speakers

  • Mark Himelstein

    Mark Himelstein

    RISC-V

    CTO

    See Bio
  • Ted Marena

    Ted Marena

    Western Digital

    Senior Director RISC-V Ecosystem, ML Business Development

  • Eric Sivertson

    Eric Sivertson

    Lattice Semiconductor

    VP Security Business

    See Bio
  • Roger Do

    Roger Do

    Lattice Semiconductor

    Senior Manager for Design Tools

    See Bio

  • Host

  • Ted Marena

    Ted Marena

    Western Digital

    Senior Director RISC-V Ecosystem, ML Business Development

  • Organizer

  • Ted Marena

    Ted Marena

    Western Digital

    Lead Organizer

    View Profile