Training Description

This is a 4-week training workshop, that covers the complete Digital IC design flow from scratch to the GDSII with hands-on experience on industry-standard tools. The training consists of three different modules.

Module 1 

This module covers:

1.  basics of Digital design using HDL.
2.  a description of Datapath, controller paradigm. 
3. Writing the test benches of hardware

This module covers:

1. Introduction to RISC-V Instruction Set Architecture.
2. How to design RISC-V-based microprocessor core.
3. Implementation of partial Instructions of RISC-V base ISA.
4. Formal verification techniques of RISC-V-based CPU core.

This module covers:

1. Introduction to physical design flow of digital IC.
2. Implementation of RTL-to-GDSII of the CPU designed in module 2.
3. Hands-on experience with industry-standard Cadence Tools.

Pre-Requisites

• Basic familiarity with Digital system design.
• Basic familiarity with HDL: Verilog or System Verilog

Target Audience

The target audience for this training program is fresh or graduate students with degree in Electrical engineering, computer science, computer engineering, or relevant discipline, who are passionate about getting into the digital design industry.

Registration 

• Number of seats: 15
• 90% funding is available for limited seats which will be based on a screening test. The remaining 10% will be reimbursed if the candidate secures 80% marks in the final evaluation.
• Register here: forms.gle/81sYHatG6sFDsQfw5
• Short-listed candidates will be contacted by the organizers.

In case of any queries, contact omarimtiaz@uet.edu.pk