RISC-V is an open ISA that is gaining more attraction every day. Every RISC-V processor implementation needs to make sure that it meets the requirements defined by the ISA spec. There are open-source test suites available to check the compliance of an implementation. These suites use a special open-source compliance framework called RISCOF, which enables the user to run the compliance tests on the implements, compare the results and give the report. 

Follow this like to learn more about RISC-V Architecture Compliance Test (ACT) suites.

Follow this link to learn more about the ACT framework: RISCOF.

In this Hackathon, participants will be porting the ACT framework on riscv implementation, meaning, running the compliance tests suite on the RISC-V processor using the RISCOF compliance framework. The following two basic requirements must be fulfilled to carry out the task. 

• Participants must be familiar with using Linux OS.
• Participants must be familiar with RISC-V implementation (at least RV32I) *

Hackathon is comprised of three days: from November 11th (Friday) to November 13th (Sunday).  

Day 1: Participants will be divided into teams. (At least 2 and at most 4 members per team). Each team must choose an HDL simulator and RISC-V processor implementation to work on. Brainstorming sessions will be conducted to implement the project.

Day 2: The goal is to create a simulation environment of the processor for compliance testing using the selected simulator.

Day 3: Enable the processor to run the compliance tests and automate the whole process using scripts. Closing: Each team will present its work at the end. Winners will be announced.

Registration Deadline: The deadline for registration is November 8th (11:59 pm PKT). In case of any queries: Please reach out to hr@10xengineers.ai

Important: We require CNIC for the verification and please bring the original CNIC with you to the venue. 

*Participants are welcome to bring their own RISC-V implementation.