RISC‑V International and TU Graz are excited to host the Community Challenge with HaDes‑V – an open, hands-on event for the global RISC‑V community. With HaDes‑V, you’ll delve into hardware design and create your own pipelined 32-bit RISC‑V microcontroller, mastering efficient computing principles and practical FPGA implementation.
HaDes‑V is an innovative Open Educational Resource (OER) designed to teach microcontroller and processor design through a step-by-step, modular approach. It provides a comprehensive Instruction Guide and an open-source template repository, empowering participants to explore RISC‑V design using industry-standard tools. The unique “jigsaw puzzle” methodology has you implement each processor stage (fetch, decode, execute, memory, write-back) individually and validate it against precompiled golden reference modules for instant feedback. This incremental approach bridges theoretical concepts with practical hardware implementation, building confidence and real-world skills as you progress. Participants only need a standard laptop to join the remote phase – no personal FPGA board is required.
To register for the challenge, please follow these steps:
Create your project repository – Set up a new GitHub or GitLab repository for your HaDes‑V Challenge project code. The project code will be provided during the live call on March 3 and updated here after that date. For now just register for the event.
Grant access – Add the HaDes‑V organizing team as collaborators with read/write access to your repo. (This enables our GIT-based auto-grading system to provide immediate feedback on your progress. More info coming soon.)
Sign up – Complete the official HaDes‑V Challenge Registration Form (included in the RSVP on this page) to confirm your participation.
February 3 2026: Pre-Challenge Announcement – Watching the video here. This provides an overview of the challenge and details about the kickoff event.
March 3 2026: Livestream Kickoff Event – Official start of the challenge with a live online introduction and Q&A session (the kickoff will be streamed and recorded for those who cannot attend live).
March 3 – May 31, 2026: Remote Development Phase – Work on the HaDes‑V exercises and develop your RISC‑V microcontroller design at your own pace, using just your laptop (no FPGA hardware is required for the remote phase). Registration closed April 3.
June 2026: - Possible in person portion with provided hardware.
Participants can earn Credly digital certificates for achieving key milestones in the challenge:
HaDes-V Bronze 🥉 Exercises 1–3 Certificate: Awarded upon successful completion of Exercises 1–3 of the HaDes‑V challenge.
HaDes-V Silver 🥈 Simulation Phase Certificate: Awarded for completing the simulation transfer section of the project (bringing your design from simulation towards hardware readiness).
HaDes-V Gold 🥇 Workshop Certificate: Awarded for participating in the on-site HaDes‑V hands-on workshop. Details TBD.
Each digital certificate can be shared on your Social media profile such as LinkedIn profile to showcase your accomplishment.
After completing the challenge, participants will be able to:
design a complete, modular RISC‑V based microcontroller unit using SystemVerilog and standard development environments
analyze the functionality and efficiency of microcontroller designs using verification, synthesis and debugging tools
implement different pipeline stages of a microcontroller using processor architecture knowledge and hardware description languages
explain the execution of software in processors and evaluate their interaction with hardware
HaDes-V Instruction Guide: https://doi.org/10.3217/nytm4-grv34
HaDes-V Template Repository: https://github.com/tscheipel/HaDes-V/
HaDes-V Paper/Poster (RISC‑V Summit Europe): https://www.researchgate.net/publication/391862217_Learning_by_Puzzling_A_Modular_Approach_to_RISC-V_Processor_Design_Education
HaDes-V Matrix Chat: https://matrix.to/#/#mdlab:chat.tugraz.at
Linux Mint 21 Virtual Machine (without the AMD Vivado toolchain; 4.5GB): https://cloud.tugraz.at/index.php/s/xFTeCnZZgca9HsJ
HaDes-V Material Hub: https://www.scheipel.com/hades-v
Graz University of Technology
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RISC-V International
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RISC-V International
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