NOTE: Hardware Track is sold out. Only a few seats left in the Software Track
This event is for developers currently working on RISC-V or interested in increasing their knowledge in the open standard. You will benefit from training sessions and hands-on workshops, moving beyond theoretical knowledge to direct application.
You’ll learn what works today, experiment with tools, and discover how RISC-V is redefining hardware and software co-design and giving you freedom to create your own solutions.
Join us and work directly with proven techniques from experts, and start building right away.
Why should you attend?
In just one day, you’ll gain high-level insights into RISC-V and practical skills you can apply immediately. Our expert-led workshops provide direct access to proven techniques, maximize interaction and questions, and equip you with the knowledge, tools, and confidence to continue building long after the event.
€30 Registration Includes:
Hardware or Software Track
Workshop Materials
Community networking
Interaction with Speakers
Lunch and Coffee Breaks
8:45 - 9:00 - Welcome Talk RISE
9:00 - 10:45 - Advanced debug and trace tools for RISC-V architectures Maurizio Menegotto, Lauterbach
10:45-11:00 Break
11:00 - 12:00 - Zephyr RTOS Debugging and Performance Analysis on RISC-V Maurizio Menegotto, Lauterbach & Benjamin Cabe, Zephyr Project
12:00 - 13:00 - Hands-on OP-TEE with Andes RISC-V Paul Ku, Andes Technology Corporation
13:00 - 14:00 - Lunch
14:00 - 15:45 - Porting SIMD to RISC-V Vectors Daniel Thompson, RISCstar Solutions
15:45 - 16:00 - Break
16:00 - 17:00 - Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline Niraj Dengale & Frank Yueh-Feng Lee, Andes Technology Co. Ltd. 17:00 - 18:00 - How to: Bringing up ExecuTorch on a RISC-V Microcontroller Jeremy Bennett, Embecosm See full workshop details under speaker name.
8:45 - 9:00 - Welcome Talk Teresa Cervero, Barcelona Super Computing
9:00 - 10:00 - From Open Silicon to Real Hardware: Hands-On RISC-V Development with Zephyr and the Puppy Microcontroller Marcelo Knorich Zuffo & Laisa Costa De Biase, Universidade de Sao Paulo
10:00 - 11:00 - Building an AI Accelerator with High-Level Synthesis Werner Bachhuber, Siemens EDA
11:00 - 12:00 - UCAgent: An End-to-End Agent for Unit-Level Chip Verification Junyue Wang, Institute of Computing Technology, CAS
12:00 - 13:00 - RISC-V Architectural Certification Tests Early Adoption Workshop Jordan Carlin & David Harris, Harvey Mudd College with Mike Thompson, OpenHW Foundation 13:00 - 14:00 - Lunch
14:00 - 15:45 - Hands-on Introduction to CHERI Alfredo Mazzinghi, CHERI Alliance Marno van der Maas & John Thomson, lowRISC
15:45 - 16:00 - Break
16:00 - 17:00 - Introduction to RISC-V in gem5 Ivan Fernandez Vega, Barcelona Supercomputing Center
17:00 - 18:00 - Building a Multi‑Guest Virtualized System with Bao on CVA6 in Automotive Joerg Seitter, Infineon Technologies AG & Sandro Pinto, OSYX Technologies
See full workshop details under speaker name.
Lauterbach
Software Track Speaker
Barcelona Supercomputing Center (Spain)
Hardware Track Speaker
Universidade de São Paulo
Software Track Speaker
University of São Paulo
Software Track Speaker
Andes Technology Corporation
Software Track Speaker
OpenHW Foundation
Hardware Track Speaker
Harvey Mudd College
Hardware Track Speaker
Embecosm
Software Track Speaker
Harvey Mudd College
Hardware Track Speaker
Institute of Computing Technology, Chinese Academy of Sciences
Hardware Track Speaker
University of Cambridge
Hardware Track Speaker
Andes Technology Corp.
Software Track Speaker
RISCstar Solutions
Software Track Speaker
OSYX Technologies
Hardware Track Speaker
Infineon Technologies AG
Hardware Track Speaker
Linux Foundation
Software Track Speaker
Andes Technology
Software Track Speaker
Siemens EDA
Hardware Track Speakers
Monday, June 8, 2026
6:30 AM – 4:00 PM (UTC)
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