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The RISC-V Mentorship Program matches mentors and project leaders together with mentees from around the globe. We are excited to share with our community the projects and experiences of our 2023 participants!
RISC-V Mentee - Addition of an Open Floating-Point to an Open RISC-V Core
Shayan Hassan Baig
RISC-V Mentee - Addition of an Open Floating-Point to an Open RISC-V Core
Kemal Kılıç
RISC-V Education Apprentice
Dev Chadha
Muhammad Mohsin Siddiqui
When
Wednesday, July 17, 2024 3:00 PM – 4:00 PM (UTC)
Agenda
RISC-V Mentorship Overview
Hear about how the mentorship process works and how you can apply now to be one of our next graduates!
Addition of an Open Floating-Point to an Open RISC-V Core
NucleusRV is a RISC-V core written in CHISEL-HDL. It is a 5 stage pipelined core supporting the M and C extensions of the 32-bit variant of the RISC-V spec. It is also used as the base core
for the SoC-Now SoC generator. However, NucleusRV lacks the computation of floating-point numbers. In order to achieve its target to be Linux capable, adding support of the RISC-V Single-Precision F Extension is a monumental milestone. Aside from being an important achievement for the project itself, it also showcases the relevance of open-source collaboration in hardware design by being able to combine and adapt free IP’s as needed.
Overcoming the Learning Curve for Novice Candidate Developers in RISC-V
This talk focuses on what aspects of the RISC-V Education Apprentice LFX Mentorship program were important in creating the RISC-V Learn repository from my perspective. The objective of this mentorship appealed to me specifically due to its core role in contributing to the RISC-V ecosystem and unleashing RISC-V's full potential, by creating an accessible and organized "learning pathway" for novice candidate developers, who will carry forward the advancement of RISC-V. The talk focuses on how the concepts of "open standard" and community driven nature of RISC-V are essential in considering the importance of an organized resource center for beginners in RISC-V, and how initial steps of this were achieved by implementing the RISC-V Learn repository. Existing strengths of RISC-V's development drivers are emphasized, and impact of resource accessibility for generating interest at the early stages of learning can multiply the impact of progress are discussed. The talk ends with an encouragement of learners to explore their ambitions in pursuing the semiconductor field, and of existing RISC-V members to contribute to the RISC-V Learn repository.
Integrating Tile Link Uncached Heavyweight in the Caravan Framework- A Journey of Enhanced Functionality
In our recent project, we successfully integrated the Tile Link UH (Uncached Heavyweight) protocol into the Caravan framework, enhancing its capabilities and performance. Tile Link UH, an advanced extension of the Tile Link UL protocol, introduces atomic and hint operations, as well as support for burst messages. This integration brings significant improvements to the Caravan framework, enabling more efficient data handling and communication. In this talk, we will delve into our journey, exploring the intricacies of the Tile Link UH protocol, the challenges we faced during integration, and the comprehensive testing and verification processes we employed. Join us as we share insights and lessons learned from this exciting project.
