
Jan 18, 2023, 3:30 – 5:00 PM (UTC)
The RISC-V Mentorship Program matches mentors and project leaders together with mentees from around the globe. We are excited to share with our community the projects and experiences of our 2022 participants!
InCore Semiconductors
Verification Engineer
Indian Institute of Technology Roorkee
Student
Usman Institute of Technology
Research Assistant
University of Tokyo
Undergraduate Student
RIOS Lab
Postdoctoral Researcher
RIOS Lab
Master's Student
University of Chinese Academy of Sciences
University of London
Undergraduate Student
Wednesday, January 18, 2023
3:30 PM – 5:00 PM (UTC)
| Opening Remarks |
| Feature Optimizations for RISC-V Compliance Test Generator (CTG) and RISC-V ISA Coverage (ISAC) |
| A Software Engineer's Journey in RISC-V |
| Implementing the Level-3 OpenBLAS Kernel using RISC-V Vector Instructions |
| Automatic Test Generation and Verification for RISC-V Vector Extension |
| No Man's Land: Security Threats in the New Architecture of Operating Systems |
| Writing High-Performance Software for RISC-V |
| Closing Remarks |
| Breakout Rooms |
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