The RISC-V Mentorship Program matches mentors and project leaders together with mentees from around the globe. We are excited to share with our community the projects and experiences of our 2022 participants!
InCore Semiconductors
Verification Engineer
Indian Institute of Technology Roorkee
Student
Usman Institute of Technology
Research Assistant
University of Tokyo
Undergraduate Student
RIOS Lab
Postdoctoral Researcher
RIOS Lab
Master's Student
University of Chinese Academy of Sciences
University of London
Undergraduate Student
Edwin Joy is a graduate from Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim, India. He currently works as a Verification Engineer at InCore Semiconductors. He has been an active open-source contributor to the RISC-V Architectural Compatibility Testing Ecosystem and verification efforts in the micro-architectural level. As an individual who has made engineering of embedded control systems a hobby through undergraduate years, he has sought out to contribute to the RISC-V movement.
Priyansh Rathi is a student at IIT Roorkee, pursuing his degree in Bachelor of Technology in Electronics and Communication Engineering. He is primarily interested in computer systems and cybersecurity. He has been an active open-source contributor, contributing to the projects under the RISC-V Architectural Testing Framework as part of his mentorship. He wishes to make open-source development his career.
Shahzaib Kashif is a Software Engineer, currently working as Research Assistant in MERL-UITU and CHISEL Developer in Intensivate. Formerly, he worked as AWS-FPGA Software Driver Developer for Cloud FPGA Emulation at “The NOVA Project”. He has been selected in RISC-V Mentorship Programme for Spring 2022. He has hands-on experience in CHISEL, RISC-V ISA, Python.
Takumi Hiraoka is a senior undergraduate in the department of Information and Communication Engineering at the University of Tokyo. His research topic is about computer architecture, and he is interested in technology related to RISC-V and LLVM.
Dr. Xi Wang is a Postdoctoral Researcher at the RISC-V International Open Source Laboratory (RIOS Lab), Tsinghua University. Dr. Wang has over 7-year experiences in RISC-V computer architecture design. His research interests include computer architecture, RISC-V processor design, memory systems, data-intensive computing, compilers, machine-learning based system optimizations, and parallel programming.
Mr. Shenwei Hu is a Master’s student at the RISC-V International Open Source Laboratory (RIOS Lab), Tsinghua University. His advisor is Dr. Zhangxi Tan and his research interests include computer architecture, RISC-V software infrastructures and toolchains.
https://www.linkedin.cn/incareer/in/ACoAAD6UBkoBsYkN-cI9ig7KVVO_cyrcRVQjJEE
P1umer is currently a Master in Cyberspace Security at the University of Chinese Academy of Sciences, and a member of the NeSE CTF team.
He is mainly engaged in browser and kernel security research, and have received several acknowledgements from Apple, Microsoft and other vendors.
Moazzam Moriani is an undergraduate in Computer Science who always loves a good problem and understanding things deeply. He has worked with parallel algorithms in the past. He enjoys contributing to open source projects and collaboration in general. In his off-time he likes to making music.
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