The RISC-V Virtual Career Fair provides general information about RISC-V, education for students looking for jobs and an opportunity for RISC-V Members to showcase their company and recruit students.
Please read and abide by the Code of Conduct for this virtual event.
RESOURCES FOR STUDENTS AND JOB SEEKERS
- Join as an individual member for free
- See open careers from RISC-V members in RISC-V related roles on https://riscv.org/careers/
- For free courses taught by RISC-V International go to Learn Online.
- Interested in a mentorship related to RISC-V? Find details on applying to be a mentor and application open dates for Mentees here.
- See training partners, our YouTube channel with hours of free videos and resources for universities on our learn page, https://riscv.org/learn/
- See the working groups portal and join groups of interest!
- RISC-V International Community event playlist on YouTube
- Check out the 1st RISC-V Certification - RISC-V Foundational Associate coming out at the end of 2022!
Design Verification Engineer
Director of Solution Engineering
VP Global Talent Acquisition
Usman Institute of Technology
Technical Program Manager
Valentina’s biography is so far from the typical one... You will find some unrelated academic background as well as professional experience - College of Music, English and French Teaching, Energy Security, Visa Support, HR, and Recruitment.
This diverse hands-on touch in different spheres is her benefit now. Recruitment is not just about hundreds of interviews or typical LinkedIn messaging, it is a way to bring together a professional with the most suitable position and make sure that such employment meets all the expectations and becomes fruitful for all sides.
So, my focus now is on:
* RISC-V Processor IP
* HW Architecture, Design, and Verification roles
* Talent Search
* In-house Recruitment
* International and Czech Hiring
* A-Z Hiring (job posts, active search, intervening process, offer negotiation, etc.)
* HR Processes (onboarding, probationary period assessment, friendly talks with employees, administrative processes, employment of foreigners, exit interviews, etc.)
* Business Partner responsibilities
* Smooth collaboration with my HR colleagues, Management, and Engineers
* Implementation from the scratch the hiring processes in the new locations (e.g. France, Germany, the UK, Greece, Spain, etc.)
Fatima Khurshid is currently working as a Design Verification Engineer in 10xEngineers based in Lahore, Pakistan. Over the past year, she has worked on the verification of a server-class RISC-V processor, involving execution and development of RISC-V ISA based test plans including privileged and advanced interrupt architecture. She is also responsible for driving ‘10x-Talks’, an initiative undertaken as part of the company’s continuous learning core value to foster learning. Prior to joining 10xEngineers, Fatima worked as an Associate Design Engineer at Lampro Mellon on the coverage closure for several of SiFive's coreIP releases. Fatima holds a degree in BSc. Electrical Engineering from the University of Engineering and Technology, Lahore.
John Min is the Director of Solution Engineering at Andes Technology. John has been working for processor companies in the Silicon Valley for the past 30 years, including at Hewlett Packard, LG, Arc, MIPS and SiFive. He has a wealth of information on processor architectures, IP and high-performance processing. John specializes in balancing the power, area and performance to yield optimized SoC. He is a graduate of University of Southern California with a degree in electrical engineering.
Tyler Moore is the VP of Global Talent Acquisition for SiFive. Tyler has spent over 20 years in the Semiconductor Industry in various HR leadership roles. Most recently he was the Head of Talent for Samsung Semiconductor, N. America. Prior roles include Director of Recruiting at Qualcomm, VP of Human Resources at Quixey, and Sr. Director of HR at TiVo. Tyler has a deep passion for building teams and organization, "There’s something special about the unique engagement that comes from career opportunities. It’s the realization that every employee can impact the direction of their team or even the entire organization. One person can be that game-changing player." Tyler is a graduate of the University of Colorado, Boulder and the University of California, San Diego. In his personal time he enjoys hiking and snowboarding with his family or surfing along the coast of California.
Zeeshan Rafique is an RTL design engineer with a strong background in Computer Architecture and Digital Logic Design. I have completed my graduation in Computer System Engineering in 2021 from Usman Institute of Technology, Karachi, Pakistan. Opensource is one of the area which inspires me a lot and it turns out the reason from me to became the RISC-V ambassador from Pakistan. I have been part of 4 tapeouts of System on Chip based on RISC-V CPU which we sent in OpenMPW shuttle. I also got selected in Google Summer of Code 2021 as a mentee and mentor one project this year. My research focus area is to improve computation speed and power optimization in hardware for Machine Learning applications.
Deborah is a senior platform engineer at SiFive, a company that specializes in producing custom IP using RISC-V, an open Instruction Set Architecture (ISA). At SiFive, she has been involved with the RISC-V Foundation and CHIPS Alliance. She currently develops tooling with Chisel, an open-source Hardware Description Language (HDL). She holds a B.S. in EECS from the University of California, Berkeley and an M.S. in ECE from Carnegie Mellon University.
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
Technical Computing Labs
Chief Hardware Architect
Technical Computing Labs
Sr. Technical Director
David Donofrio is the Chief Hardware Architect for Tactical Computing Laboratories where he is engaged in building advanced hardware generation platforms, performing architectural evaluation and creating modeling and simulation tools for HPC focused systems. David began his career at Intel Corporation where he worked on 3D Graphics Architecture for Intel's Integrated Graphics Processor. Following Intel, David joined Berkeley National Labs where he spent the next 10+ years committed to building co-design environments to enable energy efficient HPC systems and led a team composed of scientists, engineers, postdoctoral fellows and students focused on the influencing future architectures for all aspects of scientific computing.
Dr. John Leidel is the Chief Scientist and Founder of Tactical Computing Laboratories where he leads efforts in developing advanced architectural and programming model techniques for scalable high performance and data intensive computing platforms. Dr. Leidel founded Tactical Computing Labs in 2016 under the premise that commodity high performance computing hardware and software architectures would not be sufficient to meet the ever increasing demands of scalable, data intensive computing. He is currently researching the use of RISC-V in developing advanced accelerators for high performance computing, network processing and irregular algorithms. He also leads efforts at TactCompLabs in advanced compiler architectures and programming models. He currently serves as a RISC-V Foundation’s Technology Horizontal chairperson. Dr. Leidel holds a PhD in Computer Science from Texas Tech University.
Steven Yeung is a Senior Director at Andes Technology and is responsible for managing various R&D activities in North America. Steven has 20 years of work experience ranging from physical layout, digital design and verification, and CPU architecture. He is excited to be part of the dynamic and growing RISCV environment.
Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.
Learn, Advocacy, and Alliances Manager