OVERVIEW

One great workshop delivered over two half-days

 o Thursday, Nov 7, 8am-12pm PST

 o Friday, Nov 8, 8am-12pm PST

Talks will have a technical focus, aiming to cover unique aspects of soft RISC-V system design. The content will help you better understand what's happening under the hood in current systems, and discussions may help us discover future design requirements.

This is a FREE online-only workshop. Registered attendees will be provided with a Zoom link.

SOFT RISC-V SYSTEMS

Now that the open instruction set architecture of RISC-V has been adopted by all major FPGA vendors, users and vendors might begin to align their goals for CPUs, SoC systems design, and software tooling. Soft CPUs and soft SoC systems offer the most flexibility for customization, but they can also provide so much diversity that tooling becomes more difficult. Establishing common tooling, standards, interfaces, and policies helps to provide consistency needed by users for designing and supporting their soft RISC-V systems.

KEYNOTES

Exciting keynote presentations will cover all major soft processor designs:

o Loren Hobbs, Bluespec (Achronix)

o Goran Bilski, AMD,

o Charles Papon, VexiiRiscv (Efinix)

o Shreya Mehrotra, Intel

o Karl Wachswender, Lattice Semiconductor

o Ken O'Hagan, Microchip

MORE INFORMATION

https://sites.google.com/view/srvs-workshop

http://tech.riscv.org/srvs 

CALL FOR PRESENTATIONS AND POSTERS

If you would like to submit a proposal to give a 30-minute presentation or a 3-minute lightning round talk + virtual poster, please click here:

https://forms.gle/59axSepBbo4GByoY7

Submissions are encouraged for presentations from the following perspectives:

o Education: professors or students presenting experiences with teaching computer architecture using RISC-V FPGA projects

o FOSS: Free and open source offerings of RISC-V processors intended for FPGAs

o Hobbyist: non-commercial / non-professional individual projects with interesting applications, or approaches to building / using RISC-V processors on FPGAs

o Research: novel features, implementations, or applications of soft RISC-V systems

o Commercial: like research, but must have a technical (not marketing) perspective

DEADLINES

13 October -- submission of presentation/poster proposal

21 October -- notification of acceptance of presentation/proposal

7 November -- workshop registration