OVERVIEW

One great workshop delivered over two half-days

 o Thursday, Nov 7, 8am-12pm PST

 o Friday, Nov 8, 8am-12pm PST

Talks will have a technical focus, aiming to cover unique aspects of soft RISC-V system design. The content will help you better understand what's happening under the hood in current systems, and discussions may help us discover future design requirements.

This is a FREE online-only workshop. Registered attendees will be provided with a Zoom link.

SOFT RISC-V SYSTEMS

Now that the open instruction set architecture of RISC-V has been adopted by all major FPGA vendors, users and vendors might begin to align their goals for CPUs, SoC systems design, and software tooling. Soft CPUs and soft SoC systems offer the most flexibility for customization, but they can also provide so much diversity that tooling becomes more difficult. Establishing common tooling, standards, interfaces, and policies helps to provide consistency needed by users for designing and supporting their soft RISC-V systems.

KEYNOTES

Exciting keynote presentations will cover all major soft processor designs:

o Loren Hobbs, Bluespec and Raymond Nijssen, Achronix

o Goran Bilski, AMD

o Charles Papon, VexiiRiscv (partnering with Efinix)

o Shreya Mehrotra, Altera

o Karl Wachswender, Lattice Semiconductor

o Ken O'Hagan, Microchip

AGENDA

Thursday 7 November

08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Deployment with Altera's RISC-V Solution, Nios V Processors

08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core

09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering

09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions

10:00 PST (18:00 UTC) Break / Open Discussion

10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore

11:00 PST (19:00 UTC) Marc Solé Bonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores

11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction

11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Educational Purposes

Friday 8 November

08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V

08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain, Hands-on Experience for Undergraduate Computer Architecture Courses using Nios V-based Soft SoCs and Real Boards

09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix), Scalable RISC-V Processing with Achronix FPGAs and 2D Network on Chip

09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center, Open-Source HW/SW FPGA-based Shell for RISC-V Emulation

09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida, NEORV32 RISC-V for Education

09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Bremen, MicroRV32, A RISC-V Platform for Education and Research

09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer, PipelineC, A SoC in C: PipelineC HDL and RISC-V

10:00 PST (18:00 UTC) Break / Lightning Round Posters

10:30 PST (18:30 UTC) Ken O'Hagan, Microchip, Mi-V RV32 Soft RISC-V Processor

11:00 PST (19:00 UTC) Bruno Levy, INRIA, Learn-FPGA and FemtoRV: from blinky to RiscV

11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec, Catamaran: for Quick FPGA Bringup of Linux-capable RISC-V CPUs

MORE INFORMATION

https://sites.google.com/view/srvs-workshop

CALL FOR PRESENTATIONS AND POSTERS [now closed]

Submissions are encouraged for presentations from the following perspectives:

o Education: professors or students presenting experiences with teaching computer architecture using RISC-V FPGA projects

o FOSS: Free and open source offerings of RISC-V processors intended for FPGAs

o Hobbyist: non-commercial / non-professional individual projects with interesting applications, or approaches to building / using RISC-V processors on FPGAs

o Research: novel features, implementations, or applications of soft RISC-V systems

o Commercial: like research, but must have a technical (not marketing) perspective

DEADLINES

13 October -- submission of presentation/poster proposal

21 October -- notification of acceptance of presentation/proposal

7 November -- workshop registration