RISC-V Technical Session | A Framework for RISC-V SBI and ISA Extension Validation

RISC-V Synergy (Forums, Technical Talks and Webinars)

Mar 21, 1:45 – 3:15 PM


RISC-V support for kvm-unit-tests enhances platform and firmware testing, soon to be EFI-bootable, broadening its application beyond KVM to CPU validation and micro-benchmarks.

About this event

Support for RISC-V has recently been integrated into kvm-unit-tests, and the capability to run these tests from EFI-supported bootloaders will be added soon. Although the test framework's name suggests it is primarily for KVM, the unit tests themselves are mini kernels that can boot independently of a VMM, broadening their applicability to platform and firmware testing as well. We plan to utilize kvm-unit-tests as the foundation for the SBI test framework and are hopeful about extending its use to other areas, such as CPU validation and micro-benchmarks. This presentation will introduce and showcase the RISC-V kvm-unit-tests.

RISC-V Technical Sessions offers insightful discussions on the progress made within Committees, SIGs, Task Groups, HCs and RISC-V Technical Community.


  • Andrew Jones

    Ventana Micro Systems

    Principal Software Engineer


  • Rafael Sene

    RISC-V International

    Technical Program Manager

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