RISC-V Technical Session | Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors

Aug 20, 2:00 – 3:00 PM (UTC)

RISC-V Synergy (Forums, Technical Talks and Webinars)

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About this event

This Technical Session evaluates RVV 1.0 hardware and compiler maturity using assembly microbenchmarks, validated performance counters, HPC and ML workloads, and Google’s Qsim, highlighting current strengths, remaining bottlenecks in predication and complex memory access patterns, and performance differences between GCC 15 and LLVM 21.

Speaker

  • Ruimin Shi

    KTH Royal Institute of Technology

    Doctoral Student in Computer Science

Host

  • Rafael Sene

    RISC-V International

    Technical Program Manager

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