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RISC-V Technical Session | ConvBench: Benchmark for 2D Convolution Primitive Evaluation

Aug 29, 2024, 2:00 – 3:15 PM (UTC)

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RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration. RISC-V ISA delivers a new level of open, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

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