Nov 21, 3:00 – 4:15 PM (UTC)
82 RSVPs
TEE implementations on RISC-V use a security monitor (SM) for enclave isolation, employing privileged ISA instructions for memory protection. The SM, running in machine-mode, shares its layer with extensive firmware that includes third-party vendor code. Dorami is privilege separation approach isolating the SM from firmware, reducing TEE attack surfaces using existing ISA features.
The RISC-V Technical Sessions provide in-depth discussions on the advancements across RISC-V International Committees, Special Interest Groups (SIGs), Task Groups, Horizontal Committees (HCs), and the wider RISC-V technical community.
ETH Zurich
PhD Student
Microsoft
Researcher
ETH Zurich
Assistant Professor
RISC-V International
Technical Program Manager
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