RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays

Apr 2, 2:00 – 3:00 PM (UTC)

RISC-V Synergy (Forums, Technical Talks and Webinars)

About this event

This talk will present our research journey from energy-efficient RISC-V processor design toward neuromorphic computing architectures for embedded AI. It will highlight how principles from digital hardware design, processor architecture, and hardware/software co-design can be applied to build scalable, efficient neuromorphic systems. 

Speaker

  • Amir Yousefzadeh

    University of Twente

    Assistant Professor

Host

  • Rafael Sene

    RISC-V International

    Technical Program Manager

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