Stefano Di Carlo is a full professor of computer engineering at Politecnico di Torino, Department of Control and Computer Engineering, Italy. He received his Ph.D. and M.S. degrees in Computer Engineering from Politecnico di Torino in 1999 and 2003, respectively.

He has authored over 200 publications in major journals and conference proceedings on a wide range of topics. Major topics include dependable computing, artificial intelligence, systems and computational biology. His current research interests include emerging computing paradigms for reliable, and energy-efficient computing, computer architectures, neuromorphic computing, systems, and computational biology.

He is currently a member of the editorial board of IEEE Design and Test Magazine and Springer Journal of Electronic Testing (JETTA) and served in the steering committee of the IEEE Transactions on VLSI. He served as general chair of the IEEE VLSI Test Symposium in (VTS) 2020 and 2021, IEEE International Symposium on On-Line Testing and Robust System Design 2020, 2021, 2022 and

IEEE Silicon Errors in Logic – System Effects Workshop in 2021, 2022. He also served as Program Chair and member of the Organizing and Program Committee of several IEEE and ACM conferences. He is currently the vice-chair of the IEEE Test Technologies Technical Council (TTTC).

Prof. Di Carlo received a number of best paper nominations and awards at various conferences, including IEEE ISVLSI 2022, BIOINFORMATICS/BIOSTEC 2014, IEEE DDECS 2003, IEEE AQTR 2010, and 2012. He was a recipient of an IEEE Computer Society Test Technology Technical Council Outstanding Service Award in recognition of the work done to virtualize the ITC Test Week 2020 Tutorials & Workshop Program, an IEEE Computer Society Meritorious Service Award in recognition of more than 8 years of significant services for TTTC Electronic Media IEEE Computer Society in 2010, an IEEE Computer Society Outstanding Contribution Award for developing the TECA database for TC membership management in 2005. He is an IEEE Computer Society Golden Core Member, a status given to individuals that distinguished in their services within the IEEE Computer Society community, and a Senior Member of the IEEE

RISC-V Technical Session - Hardware-Based Detection of Stack Buffer Overflow Attacks on RISC-V

Jul 25, 2024, 2:00 – 3:15 PM (UTC)

Jul 25, 2024, 2:00 – 3:15 PM (UTC)