RISC-V Technical Session | Is RISC-V Ready for Machine Learning?

Jul 16, 2:00 – 3:00 PM (UTC)

RISC-V Synergy (Forums, Technical Talks and Webinars)

About this event

Cross-architecture evaluation of ML and scientific-computing workloads using HPX (C++ standard library for parallelism and concurrency), benchmarking HPX's asynchronous tasking across RISC-V, ARM, and x86, including where each architecture excels, where gaps remain, and the implications for portable high-performance software.

Paper: https://arxiv.org/html/2604.00736v2

Speaker

  • Alexander Strack

    University of Stuttgart

    Computational Engineer

Host

  • Rafael Sene

    RISC-V International

    Technical Program Manager

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