Simulators are crucial during the development of a chip, like the RISC-V accelerator designed in the European Processor Initiative project. In this presentation, we showcase the limitations of the current simulation solutions in the project and propose using QEMU with RAVE. This methodology can rapidly simulate and analyze applications running on the v1.0 and v0.7.1 versions of the RISC-V V-extension. Our plugin reports the vector and scalar instructions alongside useful information such as the vector length being used, the single-element width, and register usage, among other vectorization metrics. We provide an API used by the simulated application to control the RAVE plugin, as well as the capability to generate vectorization traces that can be analyzed using Paraver. Finally, we demonstrate the efficiency of our solution across different evaluated machines and in comparison with other simulation methods used in the European Processor Accelerator (EPAC) project.