Residue Number Systems (RNS) are parallel number systems that enable computations on large numbers. They are employed in high-performance digital signal processing devices and cryptographic applications. However, the rigidity of the instruction set architectures of market-dominant microprocessors limits the use of such number systems in software applications.

We present the impact of word-size modular arithmetic-specific RISC-V custom instructions on the software implementation of Residue Number Systems. This impact is evaluated on several RNS modular multiplication sequential algorithms, and we observe that the fastest implementation employs the Kawamura et al. base extension.

Simulations using the GEM5 simulator show that RNS modular multiplication with Kawamura's base extension is 2.76 times faster when using specific word-size modular arithmetic instructions than when using pseudo-Mersenne moduli for In-Order processors, and more than three times faster for Out-of-Order processors. Compared to x86 architectures, RISC-V simulations demonstrate that using specific instructions requires 4.5 times fewer cycles in In-Order processors and eight times fewer in Out-of-Order processors.

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