RISC-V Tech Study meeting, 2/9 Thu. 19:00 (JST)
(*) Akaria NS72, 64bit RISC-V core with Vector extension, developed by NSITEXE
Report of RISC-V Summit Dec. 2022
by Adachi and Akira @AkiraTsukamoto
(*) Tentative title. After reading "The RISC-V Reader"
by @tetsu_koba
(*) Status of SiFive page on Wikipedia
https://ja.wikipedia.org/wiki/SiFive
by Takuzen Toh
https://risc-v.connpass.com/event/272834/
Lead Organizer
Organizer
Organizer