RISC-V Spring Ecosystem Meetup: Bay Area

About this event

We look forward to updating the broader technical community on the latest progress of RISC-V.  Mark Himelstein, the CTO of RISC-V will present on the latest progress various technical tasks groups have made. In addition, Lattice Semiconductor will present on their recently announced RISC-V offerings, including their design tools and security examples using RISC-V in Lattice FPGAs.  

10-10:10 Upcoming RISC-V community event updates - Ted Marena

10:10-10:40 RISC-V technical progress - Mark Himelstein

10:40-11:00  Lattice Semicondutor RISC-V design tools & examples - Roger Do, Eric Sivertson

View the event materials.